1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming contacts on semiconductor devices and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 105 at an intermediate point during fabrication. In this example, the FinFET device 100 includes three illustrative fins 110, a gate structure 115, sidewall spacers 120, a gate cap layer 125, and an isolation material 130. The fins 110 have a three-dimensional configuration: a height, a width, and an axial length. The portions of the fins 110 covered by the gate structure 115 are the channel regions of the FinFET device 100, while the portions of the fins 110 positioned laterally outside of the spacers 120 are part of the source/drain regions of the device 100. Although not depicted, the portions of the fins 110 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition.
Over recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end that is connected to a respective metal line in the metallization layer by a conductive via. In some applications, the second end of the contact structure may be connected to a contact region of a further semiconductor-based circuit element, in which case the interconnect structure in the contact level is also referred to as a local interconnect. The contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. As the critical dimensions of the circuit elements in the device level decreased, the dimensions of metal lines, vias and contact elements were also reduced. In some cases, the increased packing density mandated the use of sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required packing density in accordance with density of circuit elements in the device level.
As device dimensions have decreased, the conductive contact elements in the contact level have to be provided with critical dimensions in the same order of magnitude. The contact elements typically represent plugs or line-type features, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas, which defines the available area for the contact regions, may be about 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy.
FIG. 2 is a simplistic plan view of an illustrative prior art FinFET device 200 that will be referenced to discuss one particular problem as it relates to the formation of contact structures on a FinFET device. In general, the FinFET device 200 is formed above an active region 205 that is defined in a semiconductor substrate by an isolation structure (not shown), such as a shallow trench isolation structure. In the depicted example, the FinFET device 200 is comprised of three illustrative fins 210 and an illustrative gate structure 215. A sidewall spacer 215A and a gate cap layer 215B may be formed so as to encapsulate the gate structure 215. The fins 210 may be either merged on unmerged. In the depicted example, the fins 210 are unmerged. The portions of the fins 210 positioned laterally outside of the spacers 215A constitute the source/drain (S/D) regions of the device 200. Also depicted are illustrative source/drain contact structures 220 (which are line-type structures that are sometimes referred to as “trench silicide” or “TS” or “CA” structures) and a gate contact structure 225 (which is sometimes referred to as a “CB” structure). The source/drain contact structures 220 may be formed as a line-type structure to ensure, to the extent possible, good contact is achieved with all of the exterior surfaces of all of the fins 210, even when assuming a “worst-case” misalignment scenario. The line-type source/drain contact structures 220 extend across the entire width 230 of the active region 205 in the gate-width direction 230 of the device 200. The space 235 between the gate contact structure 225 and the source/drain contact structures 220 must be large enough such that a short circuit cannot form between the gate contact structure 225 and one of the line-type source/drain contact structures 220. In current day devices, the distance 235 may be very small, and accordingly, the distance 240 between the active region 205 and the gate contact structure 225 may be set to be about 30-60 nm. One way to ensure that such a short circuit is not created would be to simply increase the distance 240, i.e., position the gate contact structure 225 farther away from the ends of line-type source/drain contact structures 220. Unfortunately, given the drive to ever increase packing densities, such a solution would undesirably increase the “foot-print” of the device 200, thereby resulting in an undesirable area consumption penalty.
The present disclosure is directed to various methods of forming contacts on FinFET semiconductor devices, and the resulting semiconductor devices, that may avoid, or at least reduce, the effects of one or more of the problems identified above.